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The following transfer statement specify a memory. Explain the memory operation in each case. a. R2 <--- M[AR] b. M[AR] <--- R3 c. R5 <--- M[R5]

A digital computer has a common bus system for 16 register of 32 bits each. The bus is constructed using multiplexers.

Represent the following conditional control statement by two register transfer statements with control functions. If (P=1) then (R1ßR2) else if (Q = 1) then (R1 R3)

The output of four registers R0, R1, R2 and R3 are connected through 4 to 1 line multiplexer to the inputs of a fifth register, R5. Each register is eight bit long. The required transfer are dictated by four timing variables T0 through T3 as follows:

Show the block diagram of hardware that implements the following register transfer statement: yT2 : R1  R1, R1 R2

Implement the concept of subnetting in Packet tracer and show then ARP protocol activities

Packet capture and header analysis by wire-shark