Computer Organization and Architecture
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1 |
A digital computer has a
common bus system for 16 registers of 32 bits each. The bus is constructed
with multiplexers.
a.
How
many selection inputs are there in each multiplexer? b.
What
size of multiplexers are needed? c.
How
many multiplexers are there in the bus?
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2 |
The following transfer statements
specify a memory. Explain the memory operation in each case. a.
R2ß M[AR] b.
M[AR]
ßR3 c.
R5ß M[R5]
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3 |
Draw the block diagram for
the hardware that implements the following statements:
x+yz: ARß AR+BR Where AR and BR are two
n-bit registers and x,y and z are control variables. Include the logic gates
for the control functions.
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3 |
1 |
A computer uses a memory
unit with 256K words of 32 bit each. A binary instructions code is store in
one word of memory. The instructions has four parts: an indirect bit, an
operation code, a register code part to specify one of 64 registers, and an
address part. a.
How
many bits are there in the operation code, the register code part, and the
address part? b.
Draw
instruction word formant and indicate the number of bits in each part. c.
How
many bits are there in the data and address inputs of the memory?
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2 |
The following control
inputs are active in the bus system shown in figure of Basic computer
registers connected to a common bus. For each case, specify the register
transfer that will be executed during the next clock transition.
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3 |
Consider the instruction
formants of the basic computer shown in figure of demonstration of Direct
Indirect address and the list of instructions given in table of Basic
computer instructions. For each of the following 16 bit instructions, given
the equivalent four digit hexadecimal code and explain in your words what it
is that the instruction is going to perform.
a 0001
0000 0010 0100 b 1011
0001 0010 0100 c 0111
0000 0010 0000
Answer
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4 |
1 |
The Micro programmed
control organization shown in figure has the following propagation delay
times. 40ns to generate the next address, 10 ns to transfer the address into
the control address registers, 40 ns to access the control memory ROM, 10 ns
to transfer the microinstructions into the control data register, and 40 ns
to perform the required microinstructions specified by the control word. What
is the maximum clock frequency that the control can use? What would the clock
frequency be if control data register is not used?
Answer
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2 |
The control memory as in figure
has 4096 words of 24 bit each. a.
How
many bits are there in the control address register? b.
How
many bits are there in each of the four inputs shown going into the
multiplexers? c.
What
are the number of inputs in each multiplexer and how many multiplexes are
needed?
Answer
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5 |
1 |
Using table of symbol of
Binary code of instruction, give the 9 bit micro operation field for the
following micro operations: a.
AC ß AC+1, DRßDR+1 b.
PCßPC+1, DRß M[AR] c.
DRßAC, ACßDR
Answer
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2 |
Using table of symbol of
Binary code of instruction, convert the following symbolic micro operations
to register transfer statements and to binary. a.
READ,
INCPC b.
ACTDR,
DRTAC c.
ARTPC,
DRTAC, WRITE
Answer
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6 |
1 |
A bus organized CPU has 16
registers with 32 bits in each an ALU, and a destination decoder. a.
How
many multiplexers are there in the A bus and what is the size of each
multiplexer? b.
How
many selection inputs are needed for MUX A and MUX B c.
How
many inputs and outputs are there in decoder d.
How
many inputs and outputs are there in the ALU for data, including input and
output carries?
Answer
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2 |
Specify the control word
that must be applied to the processor of ALU to implement the following micro
operations.
a.
R1ßR2+R3 b.
R4ßR4 c.
R5ßR5-1 d.
R6ß SHL R1 e.
R7ßINPUT
Answer
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3 |
Determine the micro
operations that will be executed in the processor of ALU when the following
14 bit control words are applied.
a.
00101001100101 b.
00000000000000 c.
01001001001100 d.
00000100000010 e.
11110001110000
Answer
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7 |
1 |
Convert the following
arithmetic expression from infix to reverse polish notation. a.
A*B+C*D+E*F b.
A*B+A*(B*D+C*E) c.
A+B*[C*D+E*(F+G)] d.
A*[B+C*(D+E)]
/ F*(G+H)
Answer
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2 |
Convert the following
numerical arithmetic expression into reverse polish notation and show the
stack operations for evaluating numerical result
(3+4) [10(2+6)+8]
Answer
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8 |
1 |
The memory unit of a computer
has 256K words of 32 bits each. The computer has an instruction format with
four fields: an operation code field, a mode field to specify one of seven
addressing modes, a register address field to specify one of 60 processor
registers, and a memory address. Specify the instruction format and the
number of bits in each field if the in instruction is in one memory word.
Answer
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9 |
1 |
A non-pipeline system takes
50 ns to process a task. The same task can be processed in a six-segment
pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the
pipeline for 100 tasks. What is the maximum speedup that can be achieved?
Answer
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2 |
Draw a space time diagram
for a six segment pipeline showing the time it takes to process eight tasks.
Answer
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10 |
1 |
Determine the number if
clock cycles that it takes to process 200 tasks in a six segment pipeline.
Answer
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11 |
1 |
Explain
the Booth’s algorithm with the help of flowchart also show the steps for (-7)
* (-3) using Booth’s Algorithm
Answer
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12 |
1 |
a.
How
many 128*8 RAM chips are needed to provide a memory capacity of 2048 bytes? b.
How
many lines of the address bus must be used to access 2048 bytes of memory?
How many of these lines will be common to all chips? c.
How
many lines must be decoded for chips select? Specify the size of the
decoders.
Answer
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2 |
A computer uses RAM chips
of 1024 * 1 capacity. a.
How
many chips are needed, and how should their address lines be connected to
provide a memory capacity of 1024 bytes? b.
How
many chips are needed to provide a memory capacity of 16K bytes? Explain in
words how the chips are to be connected to the address bus.
Answer
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