The output of four registers R0, R1, R2 and R3 are connected through 4 to 1 line multiplexer to the inputs of a fifth register, R5. Each register is eight bit long. The required transfer are dictated by four timing variables T0 through T3 as follows:
Q.) The output of four registers R0, R1, R2 and R3 are connected through 4 to 1 line multiplexer to the inputs of a fifth register, R5. Each register is eight bit long. The required transfer are dictated by four timing variables T0 through T3 as follows:
T0:
R5ßR0
T1:
R5ßR1
T2:
R5ßR2
T3:
R5ßR3
The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5.
T0: R5 <--- R0
T1: R5 <--- R1
Ø
T2: R5 <--- R2
Ø
T3: R5 <--- R3
Ø
The timing variable are mutually exclusive,
which means that only one variable is equal to 1 at any given time, while the
other three are equal 0. Draw a block diagram showing the hardware
implementation of the register transfers. Include the connection necessary from
the four timing variables to the selection input of multiplexers and to the
load input of register R5.
Ø Here we have used 4*1 MUX
in this circuit R0, R1, R2, R3 are inputs and R5 is the outputs from each
register 8 bit are passed two OR gate is connected to S0 to S
Ø These are 4 timing
variable T0, T1, T2, T3 which are mutually exclusion which means that only one
variable is equal to 1 at any given time while the other there are equal to 0
