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1. ACN

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The output of four registers R0, R1, R2 and R3 are connected through 4 to 1 line multiplexer to the inputs of a fifth register, R5. Each register is eight bit long. The required transfer are dictated by four timing variables T0 through T3 as follows:

Q.) The output of four registers R0, R1, R2 and R3 are connected through 4 to 1 line multiplexer to the inputs of a fifth register, R5. Each register is eight bit long. The required transfer are dictated by four timing variables T0 through T3 as follows: T0: R5 ß R0 T1: R5 ß R1 T2: R5 ß R2 T3: R5 ß R3 The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5. Ans.) T0: R5 <--- R0 T1: R5 <--- R1 Ø T2: R5 <--- R2 Ø T3: R5 <--- R3 Ø The timing variable are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal 0. Draw a block diagram showing the hardware implementatio

Show the block diagram of hardware that implements the following register transfer statement: yT2 : R1  R1, R1 R2

Q.) Show the block diagram of the hardware (Similar to fig. 4.2a) that implements the following register transfer statement: yT2: R<-- R1, R1 <-- R2 Ans.) Ø Here we have used AND gate because in the equation we can see that both the input is in multiplication so we have to use the gate accordingly Ø The output from the AND gate is transferred to the register R1 & R2 the data is transferred from R1 to R2 and from R2 to R1 Ø Both the register are connected to clock

The following transfer statement specify a memory. Explain the memory operation in each case. a. R2 <--- M[AR] b. M[AR] <--- R3 c. R5 <--- M[R5]

Q.) The following transfer statement specify a memory. Explain the memory operation in each case. a. R2 <--- M[AR] b. M[AR] <--- R3 c. R5 <--- M[R5] ANS: a) Read memory from address register value from R3 b) Value from R3 is stored into memory register c) It will firstly read the memory word specified by R5 & then transfer the value into the same register R5 this is mostly used in indirect addressing

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